Jitter is an important performance parameter in a phase-locked loop (PLL). Jitter is a variation in signal timing and is caused in part by random noise. One source of random noise is resistance in the PLL's loop filter. This random noise is converted to timing jitter by the PLL's voltage-controlled oscillator (VCO). Too much PLL jitter and/or noise can dominate the signal being processed and even cause eye closure in some cases. The result is that the PLL will not accurately track an input signal.
One method to reduce jitter is to reduce the loop filter resistance. However, reducing the loop filter resistance causes an undesirable effect of increasing PLL bandwidth. Greatly increasing a loop filter capacitance counters the loop bandwidth increases. Unfortunately, increasing loop filter capacitance in an integrated loop filter requires inefficient use of a large area on a die.
Reducing VCO gain also lowers PLL jitter. The VCO gain is a change in a VCO output frequency for a change in a VCO control voltage (Vc). The following equation determines the VCO gain:
      K    vco    =            Δ      ⁢                          ⁢      VCO      ⁢                          ⁢      Output      ⁢                          ⁢      Frequency              Δ      ⁢                          ⁢      VCO      ⁢                          ⁢      Control      ⁢                          ⁢      Voltage      Thus, lowering the VCO output frequency range and/or increasing the VCO control voltage range reduces VCO gain. However, constraints imposed by modern circuit frequency and power supply voltage requirements limit reducing the VCO gain. High frequency requirements of modern circuits limit reducing the VCO output frequency range. A low-frequency range VCO simply does not meet needs of modern circuits. Furthermore, increasing the VCO control voltage range is limited by power supply voltage requirements imposed by ever-shrinking integrated circuit process feature size. As the process feature size decreases, maximum power supply voltage also decreases, therefore reducing the VCO control voltage range. Thus, reducing the loop filter resistance is typically preferred to reducing the VCO gain to lower the PLL jitter.
What is needed is an apparatus and method to reduce the PLL jitter with minimal area increase, minimal impact on the PLL bandwidth, and/or low power consumption, as well as overcoming other shortcomings noted above.